1. Field of the Invention
The present invention relates to a semiconductor memory device, specifically a synchronous semiconductor memory device operating in synchronization with a clock and a method for controlling the same.
2. Description of the Related Art
FIG. 6 is a block diagram of a general synchronous DRAM 600. The synchronous DRAM 600 includes a memory cell array 10 included in a bank 0, a memory cell array 20 included in a bank 1, row buffers 11 and 21, row decoders 12 and 22, column buffers 15 and 25, column decoders 16 and 26, sensing amplifiers 13 and 23, column switching circuits 14 and 24, an input/output circuit 30, and a control circuit 31.
The synchronous DRAM 600 causes a command to be set or causes data to be input thereto or output therefrom in synchronization with a rising edge of a clock CLK supplied from an external device. An access time period until first data is accessed is substantially the same in the synchronous DRAM 600 and a non-synchronous DRAM. In the synchronous DRAM 600, data in a plurality of memory cells connected to one, same word line can be read at a high speed on a clock-by-clock basis.
In the synchronous DRAM 600, a pre-charge time period can be hidden by alternately reading data from the memory cell array 10 and data from the memory cell array 20.
In the case where, while the data is continuously read from the memory cells connected to one word line in the memory cell array 10, data from a memory cell connected to another word line in the memory cell array 10 is read, the synchronous DRAM 600 operates in the following manner. In the following example, the burst length is 4 and the CAS latency is 2. Bit lines in the memory cell array 10 are precharged before time t0.
FIG. 7 is a timing diagram illustrating the data output from the synchronous DRAM 600 shown in FIG. 6 in accordance with the JEDEC standards by a function of time. The components of the synchronous DRAM 600 described below are generally shown in FIG. 6.
In this specification, "(t0)" refers to a time period from time t0 to time t1; "(t1)" refers to a time period from time t1 to time t2; "(t2)" refers to a time period from time t2 to time t3; and the like.
During time periods (t0) and (t1) , the control circuit 31 instructs a row address RA01, which is a part of an address AD, to be held in the row buffer 11. The row address RA01 is decoded by the row decoder 12. As a result, one of the word lines in the memory cell array 10 is selected, and the contents stored in memory cells corresponding to one row are read to a bit line. Next, the data indicating the potential of the bit line is amplified by the sensing amplifier 13.
During time periods (t2) and (t3), the control circuit 31 instructs a column address CA01, which is a part of the address AD, to be held in the column buffer 15. The column address CA01 is decoded by the column decoder 16. As a result, data D00 indicating a potential of a bit line selected by the column decoder 16 is supplied to the input/output circuit 30 through the column switching circuit 14. The data D00 is held in a latch circuit (not shown) in the input/output circuit 30.
During a time period (t4), the data D00 is output from the latch circuit in the input/output circuit 30. In other words, at time t4, the data D00 output from the synchronous DRAM 600 can be read by an external device. The control circuit 31 supplies the column address counter in the column buffer 15 with a clock, thereby incrementing the column address in the column buffer 15. Data D01 indicating a potential of a bit line corresponding to the incremented column address is supplied to the input/output circuit 30 through the column switching circuit 14. The data D01 is held in the latch circuit in the input/output circuit 30.
An operation similar to the operation performed in the time period (t4) is repeated, and thus data D02 and data D03 are output from the input/output circuit 30 during time periods (t5) through (t7). In other words, during the time periods (t4) through (t7), continuous 4-word data D00 through D03 is output from the input/output circuit 30.
During a time period (t6), bit lines in the memory cell array 10 are precharged in preparation of the next access. According to the JEDEC standards, the contents in the row buffer 11, the column buffer 15 and in the latch circuits in the input/output circuit 30 are all cleared during the precharging. However, since one cycle of the clock CLK is as short as, for example, 10 ns, even when the synchronous DRAM 600 receives an external signal indicating the clearing at time t6, there is a delay generated from the receipt of the external signal until the execution of the clearing. Accordingly, data D03 is accurately output at time t7. The clearing is completed during a time period (t8).
During time periods (t9) and (t10), a row address RA0X and a column address CA0X are input. During time periods (t13) through (t16), continuous 4-word data DX0 through DX3 is output from the input/output circuit 30.
As can be appreciated, in a general synchronous DRAM, time periods (t8) through (t12) are wasted.